1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for performing process control adjustments based upon trench profiles.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer composed of a variety of materials may be formed above a wafer. Thereafter, a patterned layer of photoresist may be formed above the process layer using known photolithography techniques. Typically, an etch process is then performed on the process layer using the patterned layer of photoresist as a mask. This etching process results in formation of various features or objects in the process layer. Such features may be used for a gate electrode structure for transistors. Typically, shallow trench isolation (STI) structures formed on the semiconductor wafers are filled by forming silicon dioxide using tetraethoxysilane (TEOS), over the wafer and in the STI structures. The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. Photolithography steps are generally performed to form patterned layers of photoresist above one or more process layers that are to be patterned. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features, such as a polysilicon line, or opening-type features, that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a silicon substrate 210 that contains a plurality of layers 220, 230, is shown. In one embodiment, a layer of silicon nitride is added on the surface 215 of the silicon substrate 210, producing the layer 220. Trenches 240 are formed that extend through layer 220 of silicon nitride and into the silicon substrate 210. Any of a variety of etching processes may be employed to create the trench 240. The trenches 240 in the silicon substrate 210 generally have a finite trench depth 250. The trench depth 250 extends from the bottom of the trench 240 to a top surface of the semiconductor wafer. Generally, the silicon nitride layers 220 are removed in the finished product.
FIG. 2 also illustrates a pre-polished layer of silicon dioxide material deposited on the silicon substrate 210, which is represented by layer 230. Generally, TEOS, which is a source gas, is used in the deposition process. Ideally, the silicon dioxide completely fills the trench depth 250.
Maintaining predetermined trench profile characteristics, such as trench depth 250, is important in semiconductor wafer manufacturing. Trench characteristics can affect the performance of a device manufactured from a processed semiconductor wafer. For example, variations in STI structures formed on a semiconductor wafer can affect the electrical characteristics of the semiconductor wafer. This, in turn, can affect the quality of devices produced from the processed semiconductor wafers.
Controlling trench profile characteristics during semiconductor wafer processing is generally difficult. Many times, loss of control of processing of trench structures on layers of semiconductor wafers can cause excessive variations among trench structures on the semiconductor wafers 105. These variations can cause undesirable electrical characteristics associated with the operation of devices manufactured from the semiconductor wafers.
Turning now to FIG. 3, trenches 240 formed in a process layer 210 is illustrated. During processing of trench structures, loss of control can result in a trench depth 250 that is larger or smaller than a predetermined target value, or a range of values. A trench 240 with incorrect trench depth 250 can result in defective semiconductor wafers 105. Furthermore, loss of control of processing of trench structures can result in diminished ability to form trench structures that contain sidewalls 305 at the appropriate angles. The sidewall angle, xcex8, 320 can be greater or smaller than a predetermined target value, or a range of values. Variations in the sidewall angle 320 can cause undesirable fluctuations in the electrical characteristics of structures associated with the trenches 240, resulting in defective semiconductor wafers 105.
Generally, when loss of control of processing of trench structures occurs, many actions may be taken. For example, the processing chamber, e.g., etch chamber, in which the trench structures are formed, may be shut down and cleaned in an effort to return the chamber to a known steady state condition. The control of processing of trench structures is then re-initiated. However, the shutting down of a process chamber is inefficient and delays manufacturing of semiconductor wafers. Furthermore, frequent cleaning of process chambers requires a manufacturing system to constantly re-establish control of processing of trench structures from an initial state, resulting in additional delays and expenses.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for performing run-to-run control of trench profiles. At least one semiconductor wafer is processed. A trench metrology data from the processed semiconductor wafer is acquired. Data relating to at least one process chamber characteristic, the data acquired while processing the semiconductor wafer is acquired. A chamber characteristic adjustment process is performed in response to the trench metrology data and the data relating to the processing chamber characteristic. A feedback adjustment of the processing chamber characteristic is performed in response to the chamber characteristic adjustment process.
In another aspect of the present invention, a system is provided for performing run-to-run control of trench profiles. The system of the present invention comprises: a metrology data storage unit to receive trench metrology data; a chamber data storage to receive chamber characteristic data relating to a processing of a semiconductor wafer; a chamber characteristic/metrology data correlation unit operatively coupled with the metrology data storage unit and the chamber data storage unit, the chamber characteristic/metrology data correlation unit to correlate the trench metrology data with corresponding chamber characteristic data; and a chamber control model to modify a chamber characteristic during a time period of processing of a semiconductor wafer based upon the correlated trench metrology data and corresponding chamber characteristic data.